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Positional instantiation. #61

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futurehome opened this issue Apr 12, 2023 · 1 comment
Open

Positional instantiation. #61

futurehome opened this issue Apr 12, 2023 · 1 comment

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@futurehome
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Hi,

For positional instantiation, seems the first port will always be output and others will be input?

image

@drom
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drom commented Jul 16, 2023

In Verilog, any argument can be any directionality

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