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Pull requests: llvm/circt

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Pull requests list

[MooreToCore] Support moore.condintion lower to Core
#7159 opened Jun 12, 2024 by mingzheTerapines • Draft
[ImportVerilog] Support readop for memberaccess case
#7158 opened Jun 12, 2024 by mingzheTerapines Loading…
[ESI] Ensure esi-cosim.py ends in build/bin folder
#7155 opened Jun 11, 2024 by mortbopet Loading…
[Moore] Add evenOp to handle event controls. Moore
#7154 opened Jun 11, 2024 by hailongSun2000 Loading…
[ESI][PyCDE] Callback service ESI
#7153 opened Jun 11, 2024 by teqdruid Loading…
[FIRRTL] Enable StrictWire Conversion right before LowerToHW
#7151 opened Jun 10, 2024 by darthscsi Loading…
[FIRRTL][Verif][LTL] Replace ltl.disable with an enable folded into verif.assert
#7150 opened Jun 10, 2024 by dobios • Draft
10
[Arc] Add VectorizeOp canonicalization
#7146 opened Jun 8, 2024 by elhewaty • Draft
5
[WIP][Verif]Add formal test intent ops
#7145 opened Jun 8, 2024 by dobios • Draft
3 tasks done
23
[FIRRTL] Strict Instance Operation
#7143 opened Jun 7, 2024 by darthscsi Loading…
[FIRRTL] Add DPI call intrinsic and lowering pass
#7139 opened Jun 5, 2024 by uenoku Loading…
14
[FIRRTL] Remove "Forceable" interface, simplify and cleanup FIRRTL Involving the `firrtl` dialect
#7138 opened Jun 5, 2024 by dtzSiFive • Draft
[FIRRTL] Document how flow and flip are removed from the firtool pipeline.
#7134 opened Jun 5, 2024 by darthscsi Loading…
[FIRRTL] Conversion pass to create strict wires
#7133 opened Jun 5, 2024 by darthscsi Loading…
[CombFolds] Relax block optimization barrier by pulling constants Comb Involving the `comb` dialect
#7124 opened Jun 4, 2024 by fzi-hielscher • Draft
4
[ImportVerilog][MooreToCore]Lower moore.namedConstant to hw.param.value Moore
#7122 opened Jun 4, 2024 by mingzheTerapines Loading…
13
Backport parentheses fix to 1.5.x
#7121 opened Jun 4, 2024 by uenoku Loading…
[FIRRTL] Add a new sequential op interface for combinational loop detection.
#7120 opened Jun 3, 2024 by prithayan Loading…
[FIRRTL] Ops to operate on LHSType.
#7119 opened Jun 3, 2024 by darthscsi Loading…
[FIRRTL] Wires and Registers with read and write ports
#7118 opened Jun 3, 2024 by darthscsi Loading…
[FIRRTL] LHSType wrapper to indicate writable values.
#7117 opened Jun 3, 2024 by darthscsi Loading…
9
[FIRRTL][Sim] Add fopen and fclose intrinsics, add fd operand to printf
#7111 opened Jun 1, 2024 by SpriteOvO • Draft
1
6
[Verif] Fold disables into Property in LTLToCore verif
#7105 opened May 30, 2024 by dobios • Draft
[Verif] Allow for disable to be optional and infer it from property verif
#7104 opened May 29, 2024 by dobios • Draft
11
[MooreToCore] Support initial lowering to LLHD Moore
#7101 opened May 29, 2024 by mingzheTerapines • Draft
12
ProTip! Updated in the last three days: updated:>2024-06-09.