AArch64 update to LLVM 18

[Rot127]

WIP

Based on: #2313

Your checklist for this pull request

• I've documented or updated the documentation of every function and struct this PR changes. If not so I've explained why.
• I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

Generated with: capstone-engine/llvm-capstone#45

New features/instructions

New features:

AArch64_FEATURE_HasPAuthLR,
AArch64_FEATURE_HasSMEFA64,
AArch64_FEATURE_HasFPMR,
AArch64_FEATURE_HasFP8,
AArch64_FEATURE_HasFAMINMAX,
AArch64_FEATURE_HasFP8FMA,
AArch64_FEATURE_HasSSVE_FP8FMA,
AArch64_FEATURE_HasFP8DOT2,
AArch64_FEATURE_HasSSVE_FP8DOT2,
AArch64_FEATURE_HasFP8DOT4,
AArch64_FEATURE_HasSSVE_FP8DOT4,
AArch64_FEATURE_HasLUT,
AArch64_FEATURE_HasSME_LUTv2,
AArch64_FEATURE_HasSMEF8F16,
AArch64_FEATURE_HasSMEF8F32,
AArch64_FEATURE_HasSVE2orSME2,
AArch64_FEATURE_HasCHK,
AArch64_FEATURE_HasGCS,
AArch64_FEATURE_HasCPA,

New instructions:

AArch64_INS_ADDPT,
AArch64_INS_AUTIA171615,
AArch64_INS_AUTIASPPC,
AArch64_INS_AUTIB171615,
AArch64_INS_AUTIBSPPC,
AArch64_INS_BF1CVTL2,
AArch64_INS_BF1CVTLT,
AArch64_INS_BF1CVTL,
AArch64_INS_BF1CVT,
AArch64_INS_BF2CVTL2,
AArch64_INS_BF2CVTLT,
AArch64_INS_BF2CVTL,
AArch64_INS_BF2CVT,
AArch64_INS_F1CVTL2,
AArch64_INS_F1CVTLT,
AArch64_INS_F1CVTL,
AArch64_INS_F1CVT,
AArch64_INS_F2CVTL2,
AArch64_INS_F2CVTLT,
AArch64_INS_F2CVTL,
AArch64_INS_F2CVT,
AArch64_INS_FAMAX,
AArch64_INS_FAMIN,
AArch64_INS_FCVTNB,
AArch64_INS_FMLALLBB,
AArch64_INS_FMLALLBT,
AArch64_INS_FMLALLTB,
AArch64_INS_FMLALLTT,
AArch64_INS_FMLALL,
AArch64_INS_FVDOTB,
AArch64_INS_FVDOTT,
AArch64_INS_GCSPOPCX,
AArch64_INS_GCSPOPM,
AArch64_INS_GCSPOPX,
AArch64_INS_GCSPUSHM,
AArch64_INS_GCSPUSHX,
AArch64_INS_GCSSS1,
AArch64_INS_GCSSS2,
AArch64_INS_GCSSTR,
AArch64_INS_GCSSTTR,
AArch64_INS_MADDPT,
AArch64_INS_MADPT,
AArch64_INS_MLAPT,
AArch64_INS_MSUBPT,
AArch64_INS_PACIA171615,
AArch64_INS_PACIASPPC,
AArch64_INS_PACIB171615,
AArch64_INS_PACIBSPPC,
AArch64_INS_PACNBIASPPC,
AArch64_INS_PACNBIBSPPC,
AArch64_INS_RETAASPPC,
AArch64_INS_RETABSPPC,
AArch64_INS_SUBPT,

Test plan

• Fix current one.
• Add new MC tests
• Add tests for SME
• Fuzzing

General detail testing comes afterwards, when testing in general is modernized.

Closing issues

closes #2269
closes #2270
closes #2268
closes #2285

Is expected to close:

• [AArch64] Instr. with groups HasNEON, don't have HasNEONorSME and similar assigned. #2343

[hainest]

Relative to the Mar 2024 spec, the system registers listed below don't currently have a representation in Capstone. I've not yet checked to see if they are in LLVM-18's tablegen.

DBGBCR{16-63}_EL1
DBGBVR{16-63}_EL1
DBGWCR{16-63}_EL1
DBGWVR{16-63}_EL1
ICV_AP0R{0-3}_EL1
ICV_AP1R{0-3}_EL1
ICV_BPR1_EL1
ICV_CTLR_EL1
ICV_DIR_EL1
ICV_EOIR{0-1}_EL1
ICV_HPPIR{0-1}_EL1
ICV_IAR{0-1}_EL1
ICV_IGRPEN{0-1}_EL1
ICV_NMIAR1_EL1
ICV_PMR_EL1
ICV_RPR_EL1
SPMEVCNTR{16-63}_EL0
SPMEVFILT2R{16-63}_EL0
SPMEVFILTR{16-63}_EL0
SPMEVTYPER{16-63}_EL0
SP_EL3
TRBMPAM_EL1

[Rot127]

Couldn't find them in LLVM with grep as well.